IC Verificaiton Engineer
- Recruiter
- Anonymous
- Location
- Cambridge
- Salary
- Competitive
- Posted
- 10 Jan 2019
- Closes
- 25 Jan 2019
- Sectors
- Engineering
- Contract Type
- Permanent
- Hours
- Full Time
SoCode are proud to be working in partnership with a revolutionary technology firm in Cambridge who work at the cutting edge of technology and are growing at a phenomenal rate.
Due to this our client are looking to build their IC Design and Verification team and welcome the opportunity for a Senior or Principal IC Verification Engineer with SoC experience to focus primarily on verification of complex SoC devices, but also to work with the team to enhance existing Soc verification methodology using next generation verification techniques including high level verification languages.
This role may also involve many or all parts of the flow from block or system level specification and RTL design of modules for use in IC or FPGA, through functional verification, synthesis and timing closure, to silicon validation and production test.
This will require solid use of your high-level Verification Language experience (SystemVerilog preferred, or Specman E).
To be successful, you will possess the following verification techniques:
Bus functional models (BFMs)
Assertion based verification
Random test benches
Functional coverage
RTL design (VHDL or Verilog)
Experience of network/ interfaces is advantageous.
Location: Cambridge
Salary: GBP80,000 per annum
Benefits: Share options, bonus, pension scheme, and much more!
If you are interested and would like to know more, get in touch at
Due to this our client are looking to build their IC Design and Verification team and welcome the opportunity for a Senior or Principal IC Verification Engineer with SoC experience to focus primarily on verification of complex SoC devices, but also to work with the team to enhance existing Soc verification methodology using next generation verification techniques including high level verification languages.
This role may also involve many or all parts of the flow from block or system level specification and RTL design of modules for use in IC or FPGA, through functional verification, synthesis and timing closure, to silicon validation and production test.
This will require solid use of your high-level Verification Language experience (SystemVerilog preferred, or Specman E).
To be successful, you will possess the following verification techniques:
Bus functional models (BFMs)
Assertion based verification
Random test benches
Functional coverage
RTL design (VHDL or Verilog)
Experience of network/ interfaces is advantageous.
Location: Cambridge
Salary: GBP80,000 per annum
Benefits: Share options, bonus, pension scheme, and much more!
If you are interested and would like to know more, get in touch at