Graphics Design Verification Engineer

Recruiter
Apple
Location
London
Salary
Competitive
Posted
24 Nov 2016
Closes
22 Dec 2016
Sectors
Engineering, Design
Contract Type
Permanent
Hours
Full Time

Job Summary

Do your life's best work here. With the whole world watching. At Apple, great ideas and even complex challenges have a way of becoming great products, services, and customer experiences very quickly. This is a career defining opportunity to get in at the ground floor as we start up our UK team. Working with our Engineering teams in the US & Worldwide, you will work alongside world-class experts who are responsible for driving the direction of technological innovation across the globe. The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be leveraged to close testing coverage with high confidence.

Key Qualifications

- Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus
- Expertise with HDL simulators and waveform viewers
- Experience defining coverage space, writing coverage model, analyzing results
- Experience working under strict schedule deadlines with the ability to manage multiple priorities
- Graphics architecture and programming (OpenGL/OpenCL) highly desired. Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience.
- Experience with Perl, Shell scripting, Makefiles, TCL a plus
- Excellent communication skills and ability to collaborate

Description

Develop verification plans in coordination with design leads and architects Create and maintain verification test bench components and environments Generate directed and directed random tests Run simulations and debug design and environment issues Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes Create automated verification flows for block verification Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs Work with other block and core level engineers to ensure seamless verification flow

Education

BS/MS CE or EE

Additional Requirements

Some international travel will be required.