FPGA Engineer – Market Making

London (Greater)
06 Oct 2016
03 Nov 2016
Contract Type
Full Time

Title: FPGA Engineer – Market Making

Business Unit: Securities

Location: London

Company Overview:

Citadel Securities is one of the world’s largest securities dealers.  We are transforming financial markets around the world by consistently providing meaningful liquidity across equities, options, treasuries, currencies, interest rate swaps and other major asset classes.  We empower execution platforms and trading solutions that make markets work better, creating opportunities for investors.

Citadel Securities stands among the world’s most trusted, influential and impactful financial firms. The best and brightest are drawn to Citadel’s culture of meritocracy that prizes insightful research, intellectual curiosity and analytical rigor. The Citadel Securities team makes its mark every day from our offices around the world:

Chicago * New York * London * Hong Kong * Toronto * Shanghai * Shenzhen

For more information visit www.citadelsecurities.com.

About the Role

We are seeking an experienced FPGA Engineer to join our existing team and be responsible for the research, design, and implementation of FPGA solutions for Citadel’s trading businesses developing ultra-low latency trading systems.  We have a small and highly experience development team that is working on new FPGA designs in a hardware description language, performing timing analysis, validating and debugging designs for errors and efficiency.

Duties Include:

  • Working with a team on development and implementation of proprietary hardware trading systems from concept to production.
  • Create digital design and verification to maximize the efficiency and performance to process vast amounts of data across the trading systems.
  • Being involved in the design of ultra low latency, high throughput FPGA based custom financial trading systems to accelerate algorithmic trade signal generation and order execution.
  • The fast turn around and immediate feedback of operating designs, as well as evaluating latency and throughput.

Requirements include:

  • Experience in FPGA design, including the full FPGA design lifecycle including hardware architecture, RTL coding, simulation, system integration, hardware validation and testing.
  • Experience with Altera and/or Xilinx design software.
  • Experience in System Verilog and VHDL (System Verilog, Verilog, C, Bash, or Makefile).
  • Experience with FPGA synthesis tools and static timing analysis are desirable but not required.
  • Experience with C language for incorporation of software modeling features.
  • Must have strong problem solving skills, be adaptable, and be team oriented.

Education: Bachelors Degree in Electrical Engineering, Computer Engineering, or Computer Science; Masters Degree preferred.

Salary: Competitive

Closing date: 3 November 2016

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