DFT Engineer - Design for Test, Germany

An experienced DFT (Design for Test) is required to join a global Microelectronics firm based in Southern Germany. This company is undoubtedly a household name in electronics, with a highly successful track record in IC development for a wide range of market sectors.

As part of considerable expansion in Southern Germany, they are now looking to recruit an experienced DFT Engineer to join their team developing SoC (System on Chip) in 28nm / 14nm CMOS technology. Liaising with customers and analyzing their requirements, you will work with the team to develop test strategies for these highly complex circuits, taking care to install and verify test structures for logic functions, memory modules, and custom IPs.

The right candidate for this position have a very good working knowledge of all aspects of DfT design, with experience in Tetramax Synopsys / Mentor DFTAdvisor tools for the installation of DFT structures. The successful DFT Engineer will have a good knowledge of digital RTL design and verification.

Please note candidates must be eligible to work in the EU.

For details, contact Caroline Pye @ IC Resources

Our client is seeking a DFT (Design for Test) Engineer to join their SoC team in Southern Germany. Experience in the following is sought:- DFT (Design for Test), scan, ASIC Design, RTL design, Scan insertion, ATPG, JTAG, boundary scan, Memory-BIST, Tetramax / , DFTCompiler / Cadence NCSim Languages: VHDL, Verilog, Perl, TCL.