Digital Verification Engineer - System Verilog - Cambridge
- Recruiter
- IC Resources
- Location
- Cambridge, Cambridgeshire, England
- Salary
- £40 - £45 per hour + 6 months, £40-45 per hour
- Posted
- 28 Dec 2014
- Closes
- 09 Jan 2015
- Ref
- J28347
- Contact
- Rob Maw
- Sectors
- Engineering, Design, Electrical
- Contract Type
- Contract
- Hours
- Full Time
ASIC Verification contract, UVM, OVM, SystemVerilog, Constrained-random Verification - Cambridge
A very loyal client of IC Resources is currently looking for an ASIC Verification contractor for a 6 month contract based on-site in the UK. Ideally the successful candidate will be able to start at the beginning of December, however the client would be interested in profiles of candidates who could start early January.
Experience in the following skill sets would be required for the role
- System Verilog Verification
- Setting up and managing test benches using UVM / OVM
- Experience in constrained-random verification using System Verilog
- RTL Design knowledge using Verilog / VHDL
- ASIC / FPGA Verification experience is essential
If you feel you have the necessary experience to successfully complete the above project and you are currently eligible to work in the UK, then please do not hesitate to contact Rob Maw at IC Resources.
If you have any of the following skills ASIC Verification, OVM, UVM, SystemVerilog, test benches, constrained-random, Verilog, VHDL, Verilog and would be interested in a 6 month contract in the UK you could also be considered for this role.
IC Resources - enhancing intellectual capital
A very loyal client of IC Resources is currently looking for an ASIC Verification contractor for a 6 month contract based on-site in the UK. Ideally the successful candidate will be able to start at the beginning of December, however the client would be interested in profiles of candidates who could start early January.
Experience in the following skill sets would be required for the role
- System Verilog Verification
- Setting up and managing test benches using UVM / OVM
- Experience in constrained-random verification using System Verilog
- RTL Design knowledge using Verilog / VHDL
- ASIC / FPGA Verification experience is essential
If you feel you have the necessary experience to successfully complete the above project and you are currently eligible to work in the UK, then please do not hesitate to contact Rob Maw at IC Resources.
If you have any of the following skills ASIC Verification, OVM, UVM, SystemVerilog, test benches, constrained-random, Verilog, VHDL, Verilog and would be interested in a 6 month contract in the UK you could also be considered for this role.
IC Resources - enhancing intellectual capital